DOCUMENT NO. REV.NO PAGE
STANDARD
NAME
SPECIFICATION FOR APPROVAL
00 20/22
This instruction
(1) Loads a new 7-bit address into the address counter (ACC).
(2) Sets the address counter (ACC) to point to the DD-RAM.
Once the “Set DD-RAM Address” instruction has been executed, the contents of the address counter (ACC)
will be automatically modified after each access of DD-RAM, as selected by the “Entry Mode Set”
instruction.
Table-16 Valid DD-RAM address Ranges
Number of Character Address Range
1st
line
40
00H to 27H
2nd
line
40
40H to 67H
6.2.9 Read Busy Flag and Address
DB7
DB6
DB5
DB4
DB3 DB2 DB1 DB0
BF ACC
RS=0, R/W=1
The next instruction will not be accepted until BF is reset to 0.Check the BF status before the next write
operation. At the same time, the value of the address counter (ACC) in binary AAAAAAA is read out. This
address counter (ACC) is used by both CG-RAM and DD-RAM address and its value is determined by the
previous instruction. The address counter are the same as for instructions set CG-RAM address and set
DD-RAM address.
DB7
DB6
DB5
DB4
DB3 DB2 DB1 DB0
Data Read
RS=1, R/W=0
This instruction writes 8-bit binary data (DB7 to DB0) from CG-RAM or DD-RAM.
The previous designation determines whether CG-RAM or DD-RAM is to be read.
Before entering this read instruction, either CG-RAM or DD-RAM address set instruction must be
executed. If not executed, the first read data will be invalid. When serially executing read instructions, the
next address data is normally read from the second read. The address set instructions need not be executed
just before this read instruction when shifting the cursor shift instruction (when reading out DD-RAM).
The operation of the cursor shift instruction is the same as the set DD-RAM address instruction.
After a read, the entry mode automatically increases or decreases the address by 1.
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